With continuous development of semiconductor processing technology, process node is gradually decreased. Gate-last process has been widely applied, in order to achieve desired threshold voltage and improve device performance. However, when feature size (or critical dimension) of a device is further reduced, even when the gate-last process is applied, structure of a conventional metal-oxide-semiconductor field effect transistor (MOSFET) is no longer able to meet requirements for the device performance. As a type of multi-gate device, attention has been paid to fin field effect transistor (FinFET).
FIG. 1 depicts a three-dimensional schematic of a FinFET formed using conventional technology. As shown in FIG. 1, a FinFET includes a semiconductor substrate 10 that has a protruding fin 11 formed thereon. The fin 11 is generally obtained by etching the semiconductor substrate 10. The FinFET further includes a dielectric layer 12 that covers a surface of the semiconductor substrate 10 and a portion of sidewalls of the fin 11. The FinFET further includes a gate structure 13 that extends across the fin 11 to cover a portion of both of a top and sidewalls of the fin 11. The gate structure 13 includes a gate dielectric layer (not shown) and a gate electrode on the gate dielectric layer (not shown). For the FinFET, the portion of the top and both sidewalls of the fin 11 that is in contact with the gate structure 13 all becomes a channel region. That is, the FinFET has a plurality of gates, which can help to increase drive current and improve device performance.
Performance of the FinFET needs to be further improved. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.